December 8, 2010 - San Francisco, CA - At the annual International Electron Device Meeting (IEDM) the latest in technology for memory technology and optical sensors was displayed. For the past 56 years the conference has been the place where technology and manufacturing scaling was presented for the semiconductor industry. This years event was highlighted not only with a continuation of size scaling, but also of new devices & materials for increasing select aspects of performance at the current size.
The technology challenges were presented for DRAM and Flash Memory. DRAM is the main active memory for comuptuation and for servers. With the growing movement to cloud based computing to support the traffic on the internet, high performance and high reliability DRAM is in high demand. The challenge with DRAM is the specialize processing that is needed for 1T memory structure and its associated storage capacitor. The current state of the industry is a 30nm process and 4Gb DDR3 DRAMs. The effort to move to a 2Xnm process will require that the circuit move to a new vertical transistor rather than a lateral transistor which has been used since DRAM was invented. These new transistors will have to connect to a cell capacitor. In these small processes, in order to have the capacitance be larger than the parasitics in the system, the a high aspect ratio between the cap and device (>50x) is needed. This high aspect ratio has several manufacturability issues related to device and optical tolerances and systematic design.
DRAM scaling - courtesy IEEE
The overall direction was DRAM are still advancing but with a cost and a yield impact. The near term solutions will be based on increased density at the module level for high reliability applications and use solutions such as the JEDEC compliant Inphi LRDIMM.
For most consumer media players - music or video content - the primary storage format is NAND flash memory based on the smallest cell size and lowest cost per bit for a non-volatile (NV) memory. The current state of NAND Flash is a 20nm process which makes a 64Gb product. As scaling goes below 20nm there are significant challenges on uniformity of the cells due to optical variation in the line edge roughness of the patterns used to define the cell. The smaller processes also have issues with the declining thickness of the layers used for the floating gate, layer which stores the charge, and leakage on the cell. The thickness and cell size has now been reduced to the point that a programmed cell only stores about 10 electrons.
Similarly to DRAM the solution to scaling problem is being addressed by 3D devices. The technology is not manufacturing ready as yet, however it addresses several of the key issues. The 3D structures still have some issues, but they appear to be solvable. In the short term, the solution is stacking die into an MLC configuration. This allows for a higher density in the same package and memory DIMM space.
In addition to storage and processing, image capture is a major component of the new mobile lifestyle. Scaling limits are now starting to impact image capture for both video and still production. An invited paper presented by TSMC (paper 14.1) discussed trends and scaling limitations for current generation imagers. Traditional scaling has taken place in two directions - increasing overall size and imaging area/number of pixels and shrinking size of the pixels. The density and number of pixels has been increasing proportionally with shrink in pixel size - this left the next imager size unchanged while supporting better pixel counts. Just like in the memories, pixel size has started to run into size issues.
Scaling of 1.1u and 0.9um pixel - courtesy TSMC
One of the first changes for smaller pixels is the way the imagers are illuminated. For pixels smaller than 1.75um, designs change from Front Side Illumination (FSI) to Back Side Illumination (BSI). For BSI to be used, the wafers have to be thinned down to allow the light to pass through from the rear of the wafer. Current pixel sizes in production are 1.4um, 1.1um and experimentation at 0.9um. At these geometries, the pixels suffer from photo-response non-uniformity (PRNU). This leads to image degradation that related to pixel-to-pixel isolation and reflected film optimization. These factors impact the light and color sensitivity. The following image shows the color and light sensitivity impact of scaling the pixels from 1.1um to 0.9um. These images have had some compensation for scaling, but additional techniques are needed to prepare the scaled pixels for use in consumer products.
For the short term future, until these pixel scaling issues can be addressed and solved, the solution to higher speed and higher resolution are larger image sensors. This trend has resulted in 14-18MP sensors in the current consumer DSLR marketplace.
PC