February 23, 2015, ISSCC, San Francisco—Kinam Kim from Samsung Electronics gave the first plenary talk relating developments in silicon technologies and the solutions they may provide for our data-driven lines. The developments include silicon, packaging, and small chip security for IoT.
The number of connected devices already exceeds the number of people, and will continue to grow to over 50 B connected things by 2020. All of these things will generate increasing amounts of data, with a growth rate of 3 times per year. In parallel, the use of electricity will also grow, even though one of the biggest drivers—the data centers—are reducing power per server and total datacenter power is declining due to improvements in silicon and system architectures.
Silicon is still following Moore's law, and the ultimate device dimension may be about 1.5 nm for room temperature operation. So far, the smallest demonstrated device is a 3.8 nm FINFET. Lithography is capable of printing down to 3.25 nm with EUV and quad patterning. Unfortunately, the resists seem to be limited to about 8 nm, so we will need new materials and exposure capabilities to go much farther.
The industry has seen many changes in silicon technologies over time. At the 45 nm node, we got high-k and metal gate devices, and now we have FIN at 20 nm. The technology drivers are not the memories, but the larger systems like PCs, servers, and mobile devices. The technology gap for transition to other markets is dropping to the point where the gap across applications will be about 3 months for the 14 nm node. Mobile devices will lead the way to the next node with first products in 10 nm FIN technology at Samsung.
The underlying technologies will need to undergo major changes to get under 5 nm, but the changes will have to fit into the existing manufacturing infrastructure. DRAM is still the technology leader for many device structures, like capacitors which need a very high aspect ratio and at 10 nm the transistors will need to have gate-all-around topologies to manage leakage. The experiences with DRAM at 20 nm indicated that conformal high-k dielectrics will be necessary to reduce bit-line capacitance to compensate for the reduced capacity in the storage cell.
In other memory areas, NAND flash will move from scaling planar devices to higher levels of integration and vertical devices. The challenges will be in managing the very large number of etch steps, Vt windows, and other process variables. Vertical NAND offers a number of advantages over planar devices. It only needs one programming step, has much higher density, and the layer cell makes multi-bit cells easier to manage, since the larger cells can hold more electrons. A likely configuration is 4-bits per cell for a 1 Tb NAND with over 100 layers in a 3-D structure.
Not all changes will be in silicon. Packaging has the ability to hold more dice per package and a number of alternatives are viable; stacked die, package-on-package, and through-silicon vias are all already in production. Package-on-package enables higher levels of integration of diverse process technologies for CPU, DRAM, and NAND. The challenges are in minimizing power and heat management. TSV technologies enable much higher internal memory bandwidth due to shorter connections and higher DRAM densities. In addition, the internal architecture can be changed to use greater parallelism, changing I//O from 32- or 64-bits to 1K.
Imagers are getting higher resolution. The trend is for imagers to move towards a 1 micron pixel pitch from the 1.4 micron today. To get to the higher resolution, the device has to change from front-side to back-side illumination to eliminate the shadows from the metallization. The individual pixels have to be both electrically and optically isolated to reduce crosstalk. Newer imager architectures are adding in-pixel global shutters to store charge before processing and motion detection for anti-shake processing.
Mobile will become the driver for the next technologies because of the challenges with battery life. Our phones are getting more powerful and thinner, leaving no room for bigger batteries. As a result, more phones are using heterogeneous multi-processing and dynamic frequency and voltage scaling. To reduce power for most apps. The trends for mobile are for ever more data traffic up 11 ties from just last year, and higher peak data rates. The 4G data rates will increase to 75 Mb/s and 5G and 6G will probably be up to 1 Gb.
With these increases in data communications, there will be a great need for better spectral efficiency or more spectrum. An alternative is to reuse frequencies with spatial directivity and more micro-cells. Longer term, we may see a transition to mm wave bands in the 30 GHz range. These bands could use multiple antenna arrays for beam steering for point to moveable point connectivity.
The datacenter will move to more PCIe interfaces like NVMe to increase data bandwidth over that possible from SATA. In addition, in-storage compute on SSDs will help to increase performance and reduce power by a factor of 3. Visualizing all the data will take a lot of bandwidth. An HD display needs about 8 Gb/s while UHD takes about 40 and 8k will need almost 400 Gb/s bandwidth. The 8k TVs will need high-speed intra-panel interfaces to balance pixel delay times, and these interfaces will need various types of equalization and error correction.
Security will become a bigger issue. The processors, memory, SIM, NFC, and sensors all needed for processing your information and providing communications and storage are all susceptible to hacking. In addition, the IoT will provide many new access points and paths for a data breach. New encryption techniques can provide a unique ID that cannot be cloned. Incorporating encrypted silicon will reduce the possible paths to your data.