October 2012 - At the Linley networking and processor event, we had a chance to meet with Micron Technologies and discuss their high performance Networking DRAM solutions. These memories feature a reduced latency for fast random access, based on using a different internal design than from standard DRAM. The turnaround time on a data access is reduced by as much as 50% .
These DRAM3 designs are about twice the performance of the DRAM2 designs that were previously used. A challenge with the design is the fixed voltage level for the interface. As a result, the performance must be optimized in the context of a thermal budget that is set by the power levels of the interface. The thermal budget is key, as it is a high reliability memory with a 10yr typical change cycle and life cycle, and has an active managed memory design. This management layer includes the ECC for the increased reliability as well as the operating mode power and improvements in interface performance.
As the improvements for the new memories are by design rather than just process scaling, the new architectures along with the use of redundant elements allows for the reliability and data integrity from the ECC to be higher than older products. For the HPC and high speed networking applications, the 36bit bus interface protocol produces a very SRAM like application look to the memories. This SRAM like performance, at DRAM power and access, enables 40G and 100G devices to be implemented using the memory for packet buffers. This data plane application is different from stand control plane functions and memories.
The high speed and high density at the pin interface to the bus, drives these memories to be used for high speed applications suche 10:4 gearboxes for 100G applications. These 100G systems have been used, with the new Micron DRAM memories, to create a 400G network switching appliance that is organized as a 4x100G device. These memories are available in 2012.